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Communication Dans Un Congrès Année : 2012

Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing

Résumé

In multi-FPGA prototyping systems for circuit verification, serialized time-multiplexed I/O technique is used because of the limited number of I/O pins of an FPGA. The verification time depends on the number of inter-FPGA signals to share the same physical wire and be time-multiplexed. In this paper, we propose an adaptation of Pathfinder routing algorithm that minimizes the verification time of multi-FPGA systems by reducing the multiplexing ratio per physical wire. To run real experiments, we propose a large benchmark generation environment and we show that the verification system clock frequency is improved by 17% on average compared with conventional methods

Domaines

Electronique
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Dates et versions

hal-01058039 , version 1 (26-08-2014)

Identifiants

Citer

Mariem Turki, Habib Mehrez, Zied Marrakchi. Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing. 2014 International Conference on Reconfigurable computing and FPGA, Dec 2012, Cancun, Mexico. ⟨10.1109/ReConFig.2012.6416765⟩. ⟨hal-01058039⟩
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